Contacts are required in an integrated circuit device to provide electrical connections between layers or levels of the integrated circuit device. Semiconductor devices typically include a multitude of transistors, which are coupled together in particular configurations through the use of contacts.
A conventional flash memory module includes multiple memory cells. A memory cell includes a stacked gate, a drain, and a source. A drain contact electrically connects the drain of each memory cell to a conductive layer (a bit line) above the stacked gate. The conductive layer can be a aluminum layer. For a NOR type of memory array, a common/single source contact connects the source junctions of a number of memory cells. This common source contact is generally referred to as a “source rail.”
There is increasing pressure in the current semiconductor industry to achieve higher device density within a given die area. This is particularly true in memory circuit fabrication, such as a flash memory manufacture. In recent years, the number and density of these memory cells on the flash memory module has dramatically increased so that the number of memory cells on a single chip is expected to soon reach 1 Gigabit. Increases in semiconductor packing density and downsizing of individual devices has resulted in increases in circuit density. Many aspects of the semiconductor fabrication process are affected by the demand for density increases in device packing. Feature alignment from one semiconductor level to the next is of critical importance, particularly relating to the alignment of contact holes with the underlying structures with which they are to connect, such as active areas. Device miniaturization complicates the process of forming interconnect structures because in order to maintain sufficient electrical communication, the interconnect structure must be formed in exact alignment with an underlying active region. At the same time, the area of the interconnect structure interfacing with the active area must be maximized. Thus, as device sizes shrink there is less room for misalignment errors of the interconnect structure.
Device size reductions are due in part to advances in photolithography and directional (anisotropic) plasma etching. Because horizontal device feature sizes are approaching deep submicrometer dimensions, self-alignment techniques are employed to relax the alignment requirements and improve critical dimension (CD) control. One such self-alignment technique is called self-aligned contact (SAC) etching. In SAC etching, a pair of adjacent gate stacks are utilized to align an etched opening in an insulating layer.
Currently there are possible options for a flash memory module to utilize the self-aligned contact process. The first option is to limit the SAC process to the current location for making contact to both the source and the drain junctions. In this case, a scaled process would still be limited by high source rail resistance and/or excess source junction overlap with the gate stack.
The second option would be to merge a local area interconnect and the SAC process together. The problem with this option being is that you have to etch both a long slotted contact over the source junctions and discrete round contacts over the drain junctions. Etching of the SAC contact is generally very shape sensitive and etching of such multiple shapes during the self-aligned contact process can result in significant etch problems and self-aligned contact problems. In addition, the long slotted contact would be passing over both active junction regions and field isolation regions. The etch would ideally have to be selective to field isolation. This is somewhat difficult, because the material used for the field isolation and the undoped glass, under the borophosphosilicate glass (BPSG) are very similar.
The third possible option is to limit the SAC etch contact to one size only, all having a discrete round pattern. The problem with this approach is that the source contacts are not linked together and an additional shunting layer must be patterned (resulting in a second lithography level), etched (resulting in a second etch step), and formed for the source junctions (resulting in a second metal deposition and chemical-mechanical polishing (CMP)).
As device sizes are reduced, smaller dimensions are required to achieve higher packing densities. The spacing between the contacts and the gate can significantly contribute to the overall size of the flash memory cell. Simply reducing the space between the contacts and the gate makes the fabrication process less robust, more complex for the lithography process, and less cost effective due to yield loss resulting from alignment errors.
Thus, there is a need in the art to relax contact-to-gate spacing, making the SAC contact a requirement. In addition, there is a need for a flash memory with a smaller cell channel length, which will require the use of a local interconnect. Further still, there is an overall need to reduce the cost of the process flow, which in combination with all of the above, requires the memory cell fabrication process to be more robust, less complex, and more cost effective.